(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of fabricating memory devices employing floating gates having enhanced electron tunneling during erase.
(2) Description of the Prior Art
One class of semiconductor memory devices employs floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. A tunneling oxide, necessary for the erase function of the cell, is situated below the floating gate of the memory cell. Some current EEPROM devices employ a sharp polysilicon tip on the floating gate to enhance electron tunneling from the floating gate during erase, thus achieving more efficient erase characteristics.
U.S. Pat. No. 6,242,308 to Hsieh et al, U.S. Pat. No. 6,204,126 to Hsieh et al, and U.S. Pat. No. 6,117,733 to Sung et al use oxidation to form a sharp tip in the adjacent polysilicon gate. U.S. Pat. No. 5,963,806 to Sung et al undercuts the dielectric underlying the floating gate. A second polysilicon layer overlying one side of the floating gate forms a sharp tip in the undercut area. U.S. Pat. No. 6,090,668 to Lin et al uses a high pressure etching to form a slope in a polysilicon layer. A dielectric layer fills the sloping recess in the polysilicon. After patterning, the sharp edge of the slope forms a polysilicon sharp tip.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a sharp tip on a floating gate in the fabrication of integrated circuits.
Another object of the present invention is to provide an effective and very manufacturable method of forming a sharp tip on a floating gate in the fabrication of an EEPROM memory cell.
A further object of the invention is to provide a method of forming a sharp polysilicon tip on a floating gate using small polysilicon spacers.
Yet another object is to provide a method for forming an asymmetrical sharp poly tip using small polysilicon spacers.
In accordance with the objects of this invention a new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is achieved. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A control/floating gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the gate stack is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.